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19-1072; Rev 2; 5/98
+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16
_______________General Description
The MAX1248/MAX1249 10-bit data-acquisition systems combine a 4-channel multiplexer, high-bandwidth track/hold, and serial interface with high conversion speed and low power consumption. They operate from a single +2.7V to +5.25V supply, and their analog inputs are software configurable for unipolar/bipolar and single-ended/differential operation. The 4-wire serial interface connects directly to SPITM/ QSPITM and MICROWIRETM devices without external logic. A serial strobe output allows direct connection to TMS320-family digital signal processors. The MAX1248/MAX1249 use either the internal clock or an external serial-interface clock to perform successiveapproximation analog-to-digital conversions. The MAX1248 has an internal 2.5V reference, while the MAX1249 requires an external reference. Both parts have a reference-buffer amplifier with a 1.5% voltage adjustment range. These devices provide a hard-wired SHDN pin and a software-selectable power-down, and can be programmed to automatically shut down at the end of a conversion. Accessing the serial interface automatically powers up the MAX1248/MAX1249, and the quick turn-on time allows them to be shut down between all conversions. This technique can cut supply current to under 60A at reduced sampling rates. The MAX1248/MAX1249 are available in a 16-pin DIP and a very small QSOP that occupies the same board area as an 8-pin SO. For 8-channel versions of these devices, see the MAX148/MAX149 data sheet.
____________________________Features
o 4-Channel Single-Ended or 2-Channel Differential Inputs o Single +2.7V to +5.25V Operation o Internal 2.5V Reference (MAX1248) o Low Power: 1.2mA (133ksps, +3V supply) 54A (1ksps, +3V supply) 1A (power-down mode) o SPI/QSPI/MICROWIRE/TMS320-Compatible 4-Wire Serial Interface o Software-Configurable Unipolar or Bipolar Inputs o 16-Pin QSOP Package (same area as 8-pin SO)
MAX1248/MAX1249
_____________Ordering Information
PART MAX1248ACPE MAX1248BCPE MAX1248ACEE MAX1248BCEE
Contact
TEMP. RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C
PIN-PACKAGE 16 Plastic DIP 16 Plastic DIP 16 QSOP 16 QSOP
INL (LSB) 1/2 1 1/2 1
Ordering Information continued at end of data sheet. factory for availability of alternate surface-mount packages.
________________________Applications
Portable Data Logging Medical Instruments Pen Digitizers Data Acquisition Battery-Powered Instruments System Supervision
__________Typical Operating Circuit
+3V CH0 0V TO +2.5V ANALOG INPUTS VDD DGND C3 0.1F VDD
MAX1248 AGND
CH3 COM CS SCLK VREF I/O SCK (SK) MOSI (SO) MISO (SI) VSS
CPU
Pin Configuration appears at end of data sheet.
C1 4.7F REFADJ C2 0.01F
DIN DOUT SSTRB SHDN
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
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+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 MAX1248/MAX1249
ABSOLUTE MAXIMUM RATINGS
VDD to AGND, DGND .............................................. -0.3V to +6V AGND to DGND.................................................... -0.3V to +0.3V CH0-CH3, COM to AGND, DGND ............ -0.3V to (VDD + 0.3V) VREF to AGND........................................... -0.3V to (VDD + 0.3V) Digital Inputs to DGND............................................ -0.3V to +6V Digital Outputs to DGND ........................... -0.3V to (VDD + 0.3V) Digital Output Sink Current .................................................25mA Continuous Power Dissipation (TA = +70C) Plastic DIP (derate 10.53mW/C above +70C) ......... 842mW QSOP (derate 8.30mW/C above +70C) ................... 667mW CERDIP (derate 10.00mW/C above +70C) .............. 800mW Operating Temperature Ranges MAX1248_C_E/MAX1249_C_E .......................... 0C to +70C MAX1248_E_E/MAX1249_E_E........................ -40C to +85C MAX1248_MJE/MAX1249_MJE .................... -55C to +125C Storage Temperature Range ............................ -60C to +150C Lead Temperature (soldering, 10sec) ............................ +300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +5.25V; COM = 0V; fSCLK = 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX1248--4.7F capacitor at VREF pin; MAX1249--external reference, VREF = 2.500V applied to VREF pin; TA = TMIN to TMAX, unless otherwise noted.) PARAMETER DC ACCURACY (Note 1) Resolution Relative Accuracy (Note 2) Differential Nonlinearity Offset Error Gain Error (Note 3) Gain Temperature Coefficient Channel-to-Channel Offset Matching INL DNL MAX124_A MAX124_B No missing codes over temperature MAX124_A MAX124_B MAX124_A MAX124_B 0.25 0.05 SYMBOL CONDITIONS MIN 10 0.5 1.0 1 1 2 1 2 TYP MAX UNITS Bits LSB LSB LSB LSB ppm/C LSB
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 0V to 2.500Vp-p, 133ksps, 2.0MHz external clock, bipolar input mode) Signal-to-Noise + Distortion Ratio SINAD 66 dB Total Harmonic Distortion Spurious-Free Dynamic Range Channel-to-Channel Crosstalk Small-Signal Bandwidth Full-Power Bandwidth CONVERSION RATE Internal clock, SHDN = FLOAT Conversion Time (Note 5) Track/Hold Acquisition Time Aperture Delay Aperture Jitter Internal Clock Frequency External Clock Frequency 2 SHDN = FLOAT SHDN = VDD Data transfer only 0.1 0 tCONV tACQ 30 <50 1.8 0.225 2.0 2.0 Internal clock, SHDN = VDD External clock = 2MHz, 12 clocks/conversion 5.5 35 6 1.5 s ns ps MHz MHz 7.5 65 s THD SFDR 65kHz, 2.500Vp-p (Note 4) -3dB rolloff Up to the 5th harmonic -70 70 -75 2.25 1.0 dB dB dB MHz MHz
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+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.25V; COM = 0V; fSCLK = 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX1248--4.7F capacitor at VREF pin; MAX1249--external reference, VREF = 2.500V applied to VREF pin; TA = TMIN to TMAX, unless otherwise noted.) PARAMETER ANALOG/COM INPUTS Input Voltage Range, SingleEnded and Differential (Note 6) Multiplexer Leakage Current Input Capacitance INTERNAL REFERENCE (MAX1248 only, reference buffer enabled) VREF Output Voltage VREF Short-Circuit Current VREF Temperature Coefficient Load Regulation (Note 8) Capacitive Bypass at VREF Capacitive Bypass at REFADJ REFADJ Adjustment Range EXTERNAL REFERENCE AT VREF (Buffer disabled) VREF Input Voltage Range (Note 9) VREF Input Current VREF Input Resistance Shutdown VREF Input Current REFADJ Buffer-Disable Threshold EXTERNAL REFERENCE AT REFADJ Capacitive Bypass at VREF Reference-Buffer Gain REFADJ Input Current DIGITAL INPUTS (DIN, SCLK, CS, SHDN) DIN, SCLK, CS Input High Voltage DIN, SCLK, CS Input Low Voltage DIN, SCLK, CS Input Hysteresis DIN, SCLK, CS Input Leakage DIN, SCLK, CS Input Capacitance SHDN Input High Voltage SHDN Input Mid Voltage SHDN Input Low Voltage SHDN Input Current VIH VIL VHYST IIN CIN VSH VSM VSL IS SHDN = 0V or VDD VIN = 0V or VDD (Note 10) VDD - 0.4 1.1 VDD - 1.1 0.4 4.0 0.2 0.01 1 15 VDD 3.6V VDD > 3.6V 2.0 3.0 0.8 V V V A pF V V V A Internal compensation mode External compensation mode MAX1248 MAX1249 MAX1248 MAX1249 0 4.7 2.06 2.00 50 10 F V/V A VDD 0.5 VREF = 2.500V 18 1.0 100 25 0.01 10 VDD + 50mV 150 V A k A V MAX1248 0mA to 0.2mA output load Internal compensation mode External compensation mode 0 4.7 0.01 1.5 30 0.35 TA = +25C (Note 7) 2.470 2.500 2.530 30 V mA ppm/C mV F F % SYMBOL CONDITIONS Unipolar, COM = 0V Bipolar, COM = VREF / 2 On/off leakage current, VCH_ = 0V or VDD MIN TYP MAX UNITS
MAX1248/MAX1249
0 to VREF VREF / 2 0.01 1 16
V A pF
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+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 MAX1248/MAX1249
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.25V; COM = 0V; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX1248--4.7F capacitor at VREF pin; MAX1249--external reference; VREF = 2.500V applied to VREF pin, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SHDN Voltage, Floating SHDN Maximum Allowed Leakage, Mid Input DIGITAL OUTPUTS (DOUT, SSTRB) Output Voltage Low Output Voltage High Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS Positive Supply Voltage VOL VOH IL COUT VDD Operating mode, full-scale input (Note 11) Positive Supply Current IDD Full power-down IDD Supply Rejection (Note 12) PSR VDD = 5.25V VDD = 3.6V VDD = 5.25V VDD = 3.6V ISINK = 5mA ISINK = 16mA ISOURCE = 0.5mA CS = VDD CS = VDD (Note 10) 2.70 1.6 1.2 3.5 1.2 30 0.3 VDD - 0.5 0.01 10 15 5.25 3.0 2.0 15 10 70 mV A 0.4 0.8 V V A pF V mA SYMBOL VFLT SHDN = FLOAT SHDN = FLOAT CONDITIONS MIN TYP VDD / 2 100 MAX UNITS V nA
Fast power-down (MAX1248) VDD = 5.25V VDD = 2.7V to 5.25V, full-scale input, external reference = 2.500V
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+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16
TIMING CHARACTERISTICS
(VDD = +2.7V to +5.25V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Acquisition Time DIN to SCLK Setup DIN to SCLK Hold SCLK Fall to Output Data Valid CS Fall to Output Enable CS Rise to Output Disable CS to SCLK Rise Setup CS to SCLK Rise Hold SCLK Pulse Width High SCLK Pulse Width Low SCLK Fall to SSTRB CS Fall to SSTRB Output Enable CS Rise to SSTRB Output Disable SSTRB Rise to SCLK Rise SYMBOL tACQ tDS tDH tDO tDV tTR tCSS tCSH tCH tCL tSSTRB tSDV tSTR tSCK Figure 1 External clock mode only, Figure 1 External clock mode only, Figure 2 Internal clock mode only (Note 10) 0 Figure 1 Figure 1 Figure 2 100 0 200 200 240 240 240 MAX124_ _C/E MAX124_ _M 20 20 CONDITIONS MIN 1.5 100 0 200 240 240 240 TYP MAX UNITS s ns ns ns ns ns ns ns ns ns ns ns ns ns
MAX1248/MAX1249
Note 1: Tested at VDD = 2.7V; COM = 0V; unipolar single-ended input mode. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. Note 3: MAX1248--internal reference, offset nulled; MAX1249 -- external reference (VREF = +2.500V), offset nulled. Note 4: Ground "on" channel; sine wave applied to all "off" channels. Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. Note 6: The common-mode range for the analog inputs is from AGND to VDD. Note 7 Sample tested to 0.1% AQL. Note 8: External load should not change during conversion for specified accuracy. Note 9: ADC performance is limited by the converter's noise floor, typically 300Vp-p. Note 10 Guaranteed by design. Not subject to production testing. Note 11: The MAX1249 typically draws 400A less than the values shown. Note 12: Measured as |VFS(2.7V) - VFS(5.25V)|.
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+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 MAX1248/MAX1249
__________________________________________Typical Operating Characteristics
(VDD = 3.0V, VREF = 2.500V, fSCLK = 2.0MHz, CLOAD = 20pF, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1248-01
SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1248/49-02
INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
MAX1248-09
2.00 1.75 SUPPLY CURRENT (mA) 1.50 1.25
SHUTDOWN SUPPLY CURRENT (A)
CLOAD = 50pF CLOAD = 20pF
3.0 2.5 2.0 1.5 1.0 0.5
MAX1248
INTERNAL REFERENCE VOLTAGE (V)
RL = CODE = 10101010
4.0 3.5 FULL POWER-DOWN
2.5025
2.5000
MAX1249 1.00
CLOAD = 50pF CLOAD = 20pF
0.75 0.50 2.25
2.75
3.25
3.75
4.25
4.75
5.25
0 2.25
2.75
3.25
3.75 VDD (V)
4.25
4.75
5.25
2.4975 2.25
2.75
3.25
3.75
4.25
4.75
5.25
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. TEMPERATURE
MAX1247-04
SHUTDOWN CURRENT vs. TEMPERATURE
MAX1248-05
INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE
INTERNAL REFERENCE VOLTAGE, VREF VDD = 5.25V 2.500 2.499 VDD = 2.7V 2.498 2.497 2.496 2.495 2.494 VDD = 3.6V
MAX1248-06
1.3 MAX1248
2.0
2.501
SHUTDOWN CURRENT (A)
1.2 SUPPLY CURRENT (mA)
1.6
1.1
1.2
1.0 MAX1249 0.9 RLOAD = CODE = 1010101000 -60 -20 20 60 100 140
0.8
0.4
0.8
0 -60 -20 20 60 100 140 TEMPERATURE (C)
-60 -40 -20 0
20 40 60 80 100 120 140
TEMPERATURE (C)
TEMPERATURE (C)
INTERGRAL NONLINEARITY vs. SUPPLY VOLTAGE
MAX1248-07
INTEGRAL NONLINEARITY vs. TEMPERATURE
VDD = 2.7V 0.25 0.20 INL (LSB) INL (LSB) 0.15 0.10 0.05
MAX1248-08
INTEGRAL NONLINEARITY vs. CODE
0.075 0.050
MAX1248-09
0.30 0.25 0.20 INL (LSB) 0.15 0.10 0.05 MAX1249 00 2.25 2.75 3.25 3.75 4.25 4.75 MAX1248
0.30
0.100
0.025 0 -0.025
MAX1248 MAX1249
-0.050 -0.075 -0.100
0 5.25 -60 -40 -20 0 20 40 60 80 100 120 140 SUPPLY VOLTAGE (V) TEMPERATURE (C)
0
256
512 CODE
768
1024
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+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16
______________________________________________________________Pin Description
PIN 1 2-5 6 NAME VDD CH0-CH3 COM Positive Supply Voltage Sampling Analog Inputs Ground reference for analog inputs. Sets zero-code voltage in single-ended mode. Must be stable to 0.5LSB. Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1248/MAX1249 down; otherwise, the devices are fully operational. Pulling SHDN high puts the reference-buffer amplifier in internal compensation mode. Letting SHDN float puts the reference-buffer amplifier in external compensation mode. Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In internal reference mode (MAX1248 only), the reference buffer provides a 2.500V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to VDD. Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to VDD. Analog Ground Digital Ground Serial Data Output. Data is clocked out at SCLK's falling edge. High impedance when CS is high. Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX1248/MAX1249 begin the A/D conversion and goes high when the conversion is completed. In external clock mode, SSTRB pulses high for one clock period before the MSB decision. High impedance when CS is high (external clock mode). Serial Data Input. Data is clocked in at SCLK's rising edge. Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is high impedance. Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets the conversion speed. (Duty cycle must be 40% to 60%.) FUNCTION
MAX1248/MAX1249
7
SHDN
8
VREF
9 10 11 12
REFADJ AGND DGND DOUT
13
SSTRB
14 15 16
DIN CS SCLK
VDD
VDD 6k DOUT CLOAD 50pF DGND CLOAD 50pF DGND a) VOH to High-Z DOUT CLOAD 50pF DGND b) VOL to High-Z 6k
DOUT CLOAD 50pF DGND a) High-Z to VOH and VOL to VOH
DOUT
6k
6k
b) High-Z to VOL and VOH to VOL
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time
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+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 MAX1248/MAX1249
_______________Detailed Description
The MAX1248/MAX1249 analog-to-digital converters (ADCs) use a successive-approximation conversion technique and input track/hold (T/H) circuitry to convert an analog signal to a 10-bit digital output. A flexible serial interface provides easy interface to microprocessors (Ps). Figure 3 is a block diagram of the MAX1248/MAX1249. on the falling SCLK edge after the last bit of the input control word has been entered. At the end of the acquisition interval, the T/H switch opens, retaining charge on CHOLD as a sample of the signal at IN+. The conversion interval begins with the input multiplexer switching CHOLD from the positive input (IN+) to the negative input (IN-). In single-ended mode, IN- is simply COM. This unbalances node ZERO at the comparator's input. The capacitive DAC adjusts during the remainder of the conversion cycle to restore node ZERO to 0V within the limits of 10-bit resolution. This action is equivalent to transferring a charge of 16pF x [(V IN+) - (V IN-)] from C HOLD to the binary-weighted capacitive DAC, which in turn forms a digital representation of the analog input signal.
Pseudo-Differential Input
The sampling architecture of the ADC's analog comparator is illustrated in the equivalent input circuit (Figure 4). In single-ended mode, IN+ is internally switched to CH0-CH3, and IN- is switched to COM. In differential mode, IN+ and IN- are selected from two pairs: CH0/CH1 and CH2/CH3. Configure the channels with Tables 2 and 3. Please note that the codes for CH0-CH3 in the MAX1248/MAX1249 correspond to the codes for CH2-CH5 in the eight-channel (MAX148/MAX149) versions. In differential mode, IN- and IN+ are internally switched to either of the analog inputs. This configuration is pseudo-differential to the effect that only the signal at IN+ is sampled. The return side (IN-) must remain stable within 0.5LSB (0.1LSB for best results) with respect to AGND during a conversion. To accomplish this, connect a 0.1F capacitor from IN- (the selected analog input) to AGND. During the acquisition interval, the channel selected as the positive input (IN+) charges capacitor CHOLD. The acquisition interval spans three SCLK cycles and ends
CS SCLK DIN SHDN CH0 CH1 CH2 CH3 COM 15 16 14 7 2 3 4 5 6 +1.21V REFERENCE (MAX1248) 20k ANALOG INPUT MUX T/H CLOCK IN SAR ADC REF A 2.06* OUTPUT SHIFT REGISTER INPUT SHIFT REGISTER INT CLOCK CONTROL LOGIC
Track/Hold
The T/H enters its tracking mode on the falling clock edge after the fifth bit of the 8-bit control word has been shifted in. It enters its hold mode on the falling clock edge after the eighth bit of the control word has been shifted in. If the converter is set up for single-ended inputs, IN- is connected to COM, and the converter samples the "+" input. If the converter is set up for differential inputs, IN- connects to the "-" input, and the difference of |IN+ - IN-| is sampled. At the end of the conversion, the positive input connects back to IN+, and CHOLD charges to the input signal. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal's source impedance is high,
CAPACITIVE DAC VREF INPUT CHOLD MUX - + 16pF CH1 CSWITCH CH2 CH3
1 11 10 +2.500V *A 2.00 (MAX1249) VDD DGND AGND
COMPARATOR ZERO
CH0
12 13 DOUT SSTRB
RIN 9k HOLD AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL.
TRACK T/H SWITCH
OUT
COM
REFADJ 9 VREF 8
MAX1248 MAX1249
SINGLE-ENDED MODE: IN+ = CHO-CH3, IN- = COM. DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF CH0/CH1 AND CH2/CH3.
Figure 3. Block Diagram
8
Figure 4. Equivalent Input Circuit
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+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 MAX1248/MAX1249
Table 1. Control-Byte Format
BIT 7 (MSB) START BIT 7(MSB) 6 5 4 3 BIT 6 SEL2 NAME START SEL2 SEL1 SEL0 UNI/BIP BIT 5 SEL1 DESCRIPTION The first logic "1" bit after CS goes low defines the beginning of the control byte. These three bits select which of the four channels are used for the conversion (Tables 2 and 3). BIT 4 SEL0 BIT 3 UNI/BIP BIT 2 SGL/DIF BIT 1 PD1 BIT 0 (LSB) PD0
1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an analog input signal from 0V to VREF can be converted; in bipolar mode, the signal can range from -VREF / 2 to +VREF / 2. 1 = single ended, 0 = differential. Selects single-ended or differential conversions. In singleended mode, input signal voltages are referred to COM. In differential mode, the voltage difference between two channels is measured (Tables 2 and 3). Selects clock and power-down modes. PD1 PD0 Mode 0 0 Full power-down 0 1 Fast power-down (MAX1248 only) 1 0 Internal clock mode 1 1 External clock mode
2
SGL/DIF
1 0(LSB)
PD1 PD0
the acquisition time lengthens, and more time must be allowed between conversions. The acquisition time, tACQ, is the maximum time the device takes to acquire the signal, and is also the minimum time needed for the signal to be acquired. It is calculated by: tACQ = 7.6 x (RS + RIN) x 16pF where RIN = 9k, RS = the source impedance of the input signal, and tACQ is never less than 1.5s. Note that source impedances below 3k do not significantly affect the ADC's AC performance. Higher source impedances can be used if a 0.01F capacitor is connected to the individual analog inputs. Note that the input capacitor forms an RC filter with the input source impedance, limiting the ADC's signal bandwidth.
Analog Input Protection
Internal protection diodes, which clamp the analog input to VDD and AGND, allow the channel input pins to swing from AGND - 0.3V to V DD + 0.3V without damage. However, for accurate conversions near full scale, the inputs must not exceed VDD by more than 50mV or be lower than AGND by 50mV. If the analog input exceeds 50mV beyond the supplies, do not forward bias the protection diodes of off channels over 4mA.
How to Start a Conversion
A conversion is started by clocking a control byte into DIN. With CS low, each rising edge on SCLK clocks a bit from DIN into the MAX1248/MAX1249's internal shift register. After CS falls, the first arriving logic "1" bit defines the control byte's MSB. Until this first "start" bit arrives, any number of logic "0" bits can be clocked into DIN with no effect. Table 1 shows the control-byte format. The MAX1248/MAX1249 are compatible with SPI/QSPI and MICROWIRE devices. For SPI, select the correct clock polarity and sampling edge in the SPI control registers: set CPOL = 0 and CPHA = 0. MICROWIRE, SPI, and QSPI all transmit a byte and receive a byte at the same time. Using the Typical Operating Circuit, the sim9
Input Bandwidth
The ADC's input tracking circuitry has a 2.25MHz small-signal bandwidth, so it is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC's sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended.
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+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 MAX1248/MAX1249
D Table 2. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
SEL2 0 1 0 1 SEL1 0 0 1 1 SEL0 1 1 0 0 CH0 + CH1 + + + CH2 CH3 COM - - - -
D Table 3. Channel Selection in Differential Mode (SGL/DIF = 0)
SEL2 0 0 1 1 SEL1 0 1 0 1 SEL0 1 0 1 0 - + - + CH0 + CH1 - CH2 + CH3 -
plest software interface requires only three 8-bit transfers to perform a conversion (one 8-bit transfer to configure the ADC, and two more 8-bit transfers to clock out the 10-bit conversion result). See Figure 19 for MAX1248/ MAX1249 QSPI connections.
serial-clock frequency and the amount of idle time between 8-bit transfers. To avoid excessive T/H droop, make sure the total conversion time does not exceed 120s.
Simple Software Interface Make sure the CPU's serial interface runs in master mode so the CPU generates the serial clock. Choose a clock frequency from 100kHz to 2MHz.
1) Set up the control byte for external clock mode and call it TB1. TB1 should be of the format: 1XXXXX11 binary, where the Xs denote the particular channel and conversion mode selected. 2) Use a general-purpose I/O line on the CPU to pull CS low. 3) Transmit TB1 and, simultaneously, receive a byte and call it RB1. Ignore RB1. 4) Transmit a byte of all zeros ($00 hex) and, simultaneously, receive byte RB2. 5) Transmit a byte of all zeros ($00 hex) and, simultaneously, receive byte RB3. 6) Pull CS high. Figure 5 shows the timing for this sequence. Bytes RB2 and RB3 contain the result of the conversion padded with one leading zero, two sub-bits, and three trailing zeros. The total conversion time is a function of the
Digital Output In unipolar input mode, the output is straight binary (Figure 16). For bipolar inputs, the output is two's complement (Figure 17). Data is clocked out at the falling edge of SCLK in MSB-first format.
Clock Modes
The MAX1248/MAX1249 may use either an external serial clock or the internal clock to perform the successive-approximation conversion. In both clock modes, the external clock shifts data in and out of the MAX1248/MAX1249. The T/H acquires the input signal as the last three bits of the control byte are clocked into DIN. Bits PD1 and PD0 of the control byte program the clock mode. Figures 6-9 show the timing characteristics common to both modes.
External Clock In external clock mode, the external clock not only shifts data in and out, it also drives the analog-to-digital conversion steps. SSTRB pulses high for one clock period after the last bit of the control byte. Successive-approximation bit decisions are made and appear at DOUT on each of the next 10 SCLK falling edges (Figure 5). SSTRB and DOUT go into a high-impedance state when
10
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+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 MAX1248/MAX1249
CS tACQ SCLK
1 4 8 UNI/ SGL/ PD1 PD0 BIP DIF 12 16 20 24
DIN
START
SEL2 SEL1 SEL0
SSTRB RB1 DOUT ACQUISITION 1.5s (fCLK = 2MHz)
B9 MSB B8 B7
RB2
B6 B5 B4 B3 B2 B1 B0 LSB S1
RB3
S0
FILLED WITH ZEROS
A/D STATE
IDLE
CONVERSION
IDLE
Figure 5. 24-Clock External Clock Mode Conversion Timing (MICROWIRE and SPI-Compatible, QSPI-Compatible with fSCLK 2MHz)
CS
***
tCSH SCLK
tCSS
tCL
tCH
tCSH
*** tDS tDH
DIN tDV DOUT
*** tDO *** tTR
Figure 6. Detailed Serial-Interface Timing
CS goes high; after the next CS falling edge, SSTRB will output a logic low. Figure 7 shows the SSTRB timing in external clock mode. The conversion must complete in some minimum time, or droop on the sample-and-hold capacitors may degrade conversion results. Use internal clock mode if
the serial-clock frequency is less than 100kHz, or if serial-clock interruptions could cause the conversion interval to exceed 120s.
______________________________________________________________________________________
11
+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 MAX1248/MAX1249
CS tSDV SSTRB *** *** *** *** tSTR
tSSTRB
tSSTRB
SCLK
** * *
****
PD0 CLOCKED IN
Figure 7. External Clock Mode SSTRB Detailed Timing
CS
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
18
19
20
21
22
23
24
DIN
START
SEL2 SEL1 SEL0 UNI/ SGL/ PD1 PD0 BIP DIF
SSTRB tCONV DOUT ACQUISITION 1.5s CONVERSION 7.5s MAX
B9 MSB B8 B7 B0 LSB S1 S0
FILLED WITH ZEROS
A/D STATE
IDLE
IDLE
(fSCLK = 2MHz) (SHDN = FLOAT)
Figure 8. Internal Clock Mode Timing
Internal Clock In internal clock mode, the MAX1248/MAX1249 generate their own conversion clocks internally. This frees the P from the burden of running the SAR conversion clock and allows the conversion results to be read back at the processor's convenience, at any clock rate from 0MHz to 2MHz. SSTRB goes low at the start of the conversion and then goes high when the conversion is complete. SSTRB is low for a maximum of 7.5s (SHDN = FLOAT), during which time SCLK should remain low for best noise performance. An internal register stores data when the conversion is in progress. SCLK clocks the data out of this register at any time after the conversion is complete. After SSTRB goes high, the next falling clock edge produces the
12
MSB of the conversion at DOUT, followed by the remaining bits in MSB-first format (Figure 8). CS does not need to be held low once a conversion is started. Pulling CS high prevents data from being clocked into the MAX1248/MAX1249 and three-states DOUT, but it does not adversely affect an internal clock mode conversion already in progress. When internal clock mode is selected, SSTRB does not go into a high-impedance state when CS goes high. Figure 9 shows the SSTRB timing in internal clock mode. In this mode, data can be shifted in and out of the MAX1248/MAX1249 at clock rates exceeding 2.0MHz if the minimum acquisition time, tACQ, is kept above 1.5s.
______________________________________________________________________________________
+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16
Data Framing
The falling edge of CS does not start a conversion. The first logic high clocked into DIN is interpreted as a start bit and defines the first bit of the control byte. A conversion starts on the falling edge of SCLK, after the eighth bit of the control byte (the PD0 bit) is clocked into DIN. The start bit is defined as: The first high bit clocked into DIN with CS low any time the converter is idle; e.g., after VDD is applied. OR The first high bit clocked into DIN after bit 3 of a conversion in progress is clocked onto the DOUT pin. If CS is toggled before the current conversion is complete, the next high bit clocked into DIN is recognized as a start bit; the current conversion is terminated, and a new one is started. The fastest the MAX1248/MAX1249 can run with CS held low between conversions is 15 clocks per conversion. Figure 10a shows the serial-interface timing necessary to perform a conversion every 15 SCLK cycles in external clock mode. If CS is tied low and SCLK is continuous, guarantee a start bit by first clocking in 16 zeros. Most microcontrollers require that conversions occur in multiples of 8 SCLK clocks; 16 clocks per conversion is typically the fastest that a microcontroller can drive the MAX1248/MAX1249. Figure 10b shows the serial-interface timing necessary to perform a conversion every 16 SCLK cycles in external clock mode.
MAX1248/MAX1249
__________ Applications Information
Power-On Reset
When power is first applied, and if SHDN is not pulled low, internal power-on reset circuitry activates the MAX1248/MAX1249 in internal clock mode, ready to convert with SSTRB = high. After the power supplies have stabilized, the internal reset time is 10s, and no conversions should be performed during this phase. SSTRB is high on power-up and, if CS is low, the first logical 1 on DIN is interpreted as a start bit. Until a conversion takes place, DOUT shifts out zeros (also see Table 4).
Reference-Buffer Compensation
In addition to its shutdown function, SHDN selects internal or external compensation. The compensation affects both power-up time and maximum conversion speed. The 100kHz minimum clock rate is limited by droop on the sample-and-hold, and is independent of the compensation used.
CS
*** tCONV tCSH *** tSSTRB tSCK tCSS
SSTRB
SCLK
*** tDO PD0 CLOCK IN
DOUT
*** NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
Figure 9. Internal Clock Mode SSTRB Detailed Timing
______________________________________________________________________________________ 13
+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 MAX1248/MAX1249
CS 1 SCLK DIN DOUT SSTRB S CONTROL BYTE 0 S CONTROL BYTE 1 S CONTROL BYTE 2 8 1 8 1
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0 CONVERSION RESULT 0
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0 CONVERSION RESULT 1
Figure 10a. External Clock Mode, 15 Clocks/Conversion Timing
CS SCLK DIN DOUT S CONTROL BYTE 0 S CONTROL BYTE 1 B9 B8 B7 B6
*** *** *** ***
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0 CONVERSION RESULT 0
CONVERSION RESULT 1
Figure 10b. External Clock Mode, 16 Clocks/Conversion Timing
Float SHDN to select external compensation. The Typical Operating Circuit uses a 4.7F capacitor at VREF. A value of 4.7F or greater ensures referencebuffer stability and allows converter operation at the 2MHz full clock speed. External compensation increases power-up time (see Choosing Power-Down Mode and Table 4). Pull SHDN high to select internal compensation. Internal compensation requires no external capacitor at VREF and allows for the shortest power-up times. The maximum clock rate is 2MHz in internal clock mode and 400kHz in external clock mode.
Choosing Power-Down Mode
You can save power by placing the converter in a lowcurrent shutdown state between conversions. Select full power-down or fast power-down mode via bits 1 and 0 of the DIN control byte with SHDN high or floating (Tables 1 and 5). In both software power-down modes, the serial interface remains operational, but the ADC does not convert. Pull SHDN low at any time to shut down the converter completely. SHDN overrides bits 1 and 0 of the control byte.
Full power-down mode turns off all chip functions that draw quiescent current, reducing supply current typically to 2A. Fast power-down mode turns off all circuitry except the bandgap reference. With fast power-down mode, the supply current is 30A. Power-up time can be shortened to 5s in internal compensation mode. Table 4 shows how the choice of reference-buffer compensation and power-down mode affects both power-up delay and maximum sample rate. In external compensation mode, power-up time is 20ms with a 4.7F compensation capacitor when the capacitor is initially fully discharged. From fast power-down, start-up time can be eliminated by using low-leakage capacitors that do not discharge more than 1/2LSB while shut down. In powerdown, leakage currents at VREF cause droop on the reference bypass capacitor. Figures 11a and 11b show the various power-down sequences in both external and internal clock modes.
14
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+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 MAX1248/MAX1249
Table 4. Typical Power-Up Delay Times
REFERENCE BUFFER Enabled Enabled Enabled Enabled Disabled Disabled REFERENCE-BUFFER COMPENSATION MODE Internal Internal External External -- -- VREF CAPACITOR (F) -- -- 4.7 4.7 -- -- POWER-DOWN MODE Fast Full Fast Full Fast Full POWER-UP DELAY (s) 5 300 See Figure 13c See Figure 13c 2 2 MAXIMUM SAMPLING RATE (ksps) 26 26 133 133 133 133
CLOCK MODE SHDN SETS EXTERNAL CLOCK MODE DIN
SXXXXX11
EXTERNAL
EXTERNAL
SETS SOFTWARE POWER-DOWN
SXXXXX00
SETS EXTERNAL CLOCK MODE
SXX XXX1 1
DOUT
10+2 DATA BITS
10+2 DATA BITS
VALID DATA
INVALID DATA HARDWARE POWERDOWN
MODE
POWERED UP SOFTWARE POWER-DOWN
POWERED UP
POWERED UP
Figure 11a. Timing Diagram Power-Down Modes, External Clock
CLOCK MODE
INTERNAL SETS INTERNAL CLOCK MODE
SXXXXX10 SXXXXX00
SETS POWER-DOWN
S
DIN
DOUT
DATA VALID
DATA VALID
SSTRB MODE
CONVERSION POWERED UP
CONVERSION POWER-DOWN POWERED UP
Figure 11b. Timing Diagram Power-Down Modes, Internal Clock
______________________________________________________________________________________ 15
+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 MAX1248/MAX1249
Table 5. Software Power-Down and Clock Mode
PD1 0 0 1 1 PD0 0 1 0 1 DEVICE Full Power-Down Fast Power-Down Internal Clock External Clock
IDD (A) 100 4 CHANNELS 10 1 CHANNEL 1 1000 10,000 VREF = VDD = 3.0V RLOAD = CODE = 1010101000
Table 6. Hardware Power-Down and Internal Clock Frequency
SHDN STATE 1 Floating 0 DEVICE MODE Enabled Enabled PowerDown REFERENCEBUFFER COMPENSATION Internal External N/A INTERNAL CLOCK FREQUENCY 225kHz 1.8MHz N/A
0.1 0.1 1 10 100 1k 10k 100k 1M CONVERSION RATE (Hz)
Figure 12. Average Supply Current vs. Conversion Rate with External Reference
Software Power-Down Software power-down is activated using bits PD1 and PD0 of the control byte. As shown in Table 5, PD1 and PD0 also specify the clock mode. When software shutdown is asserted, the ADC operates in the last specified clock mode until the conversion is complete. Then the ADC powers down into a low quiescent-current state. In internal clock mode, the interface remains active, and conversion results may be clocked out after the MAX1248/MAX1249 enter a software power-down. The first logical 1 on DIN is interpreted as a start bit and powers up the MAX1248/MAX1249. Following the start bit, the data input word or control byte also determines clock mode and power-down states. For example, if the DIN word contains PD1 = 1, then the chip remains powered up. If PD0 = PD1 = 0, a power-down resumes after one conversion. Hardware Power-Down Pulling SHDN low places the converter in hardware power-down (Table 6). Unlike software power-down mode, the conversion is not completed; it stops coincidentally with SHDN being brought low. SHDN also controls the clock frequency in internal clock mode. Letting SHDN float sets the internal clock frequency to 1.8MHz. When returning to normal operation with SHDN floating, there is a tRC delay of approximately 2M x CL, where CL is the capacitive loading on the SHDN pin. Pulling SHDN high sets the internal clock frequency to 225kHz.
This feature eases the settling-time requirement for the reference voltage. With an external reference, the MAX1248/MAX1249 can be considered fully powered up within 2s of actively pulling SHDN high.
Power-Down Sequencing
The MAX1248/MAX1249 auto power-down modes can save considerable power when operating at less than maximum sample rates. Figures 12, 13a, and 13b show the average supply current as a function of the sampling rate. The following discussion illustrates the various power-down sequences. Lowest Power at up to 500 Conversions/Channel/Second The following examples illustrate two different powerdown sequences. Other combinations of clock rates, compensation modes, and power-down modes may give lowest power consumption in other applications. Figure 13a depicts the MAX1248 power consumption for one or eight channel conversions, utilizing full power-down mode and internal-reference compensation. A 0.01F bypass capacitor at REFADJ forms an RC filter with the internal 20k reference resistor with a 0.2ms time constant. To achieve full 10-bit accuracy, 8 time constants or 1.6ms are required after power-up. Waiting 1.6ms in FASTPD mode instead of in full powerup can reduce the power consumption by a factor of 10 or more. This is achieved by using the sequence shown in Figure 14.
16
______________________________________________________________________________________
+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 MAX1248/MAX1249
100 AVERAGE SUPPLY CURRENT (A) RLOAD = CODE = 1010101000
10,000 AVERAGE SUPPLY CURRENT (A) RLOAD = CODE = 1010101000 1000
10
4 CHANNELS
100
4 CHANNELS 1 CHANNEL
10
1 CHANNEL 1 0.01 0.1 1 10 100 1k CONVERSION RATE (Hz) 1 0.1 1 10 100 1k 10k 100k 1M CONVERSION RATE (Hz)
Figure 13a. MAX1248 Supply Current vs. Conversion Rate, FULLPD
Figure 13b. MAX1248 Supply Current vs. Conversion Rate, FASTPD
POWER-UP DELAY (ms)
Lowest Power at Higher Throughputs Figure 13b shows the power consumption with external-reference compensation in fast power-down, with one and four channels converted. The external 4.7F compensation requires a 75s wait after power-up with one dummy conversion. This circuit combines fast multi-channel conversion with lowest power consumption possible. Full power-down mode may provide increased power savings in applications where the MAX1248/MAX1249 are inactive for long periods of time, but where intermittent bursts of high-speed conversions are required.
3.0 2.5 2.0 1.5 1.0 0.5 0 0 0.01 0.1 1 10 TIME IN SHUTDOWN (sec)
Internal and External References
The MAX1248 can be used with an internal or external reference voltage, whereas an external reference is required for the MAX1249. An external reference can be connected directly at VREF or at the REFADJ pin. An internal buffer is designed to provide 2.5V at VREF for both the MAX1248 and the MAX1249. The MAX1248's internally trimmed 1.21V reference is buffered with a gain of 2.06. The MAX1249's REFADJ pin is also buffered with a gain of 2.06 to scale an external 1.25V reference at REFADJ to 2.5V at VREF.
Figure 13c. Typical Reference-Buffer Power-Up Delay vs. Time in Shutdown
Internal Reference (MAX1248) The MAX1248's full-scale range with the internal reference is 2.5V with unipolar inputs and 1.25V with bipolar inputs. The internal-reference voltage is adjustable to 1.5% with the circuit of Figure 15.
______________________________________________________________________________________ 17
+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 MAX1248/MAX1249
COMPLETE CONVERSION SEQUENCE 1.6ms WAIT DIN (ZEROS) 1 FULLPD 1.21V REFADJ 0V 2.50V VREF 0V tBUFFEN 75s = RC = 20k x CREFADJ 00 1 FASTPD 01 1 NOPD CH1 11 1 CH7 00 FULLPD (ZEROS) 1 FASTPD 01
Figure 14. MAX1248 FULLPD/FASTPD Power-Up Sequence
External Reference With both the MAX1248 and MAX1249, an external reference can be placed at either the input (REFADJ) or the output (VREF) of the internal reference-buffer amplifier. The REFADJ input impedance is typically 20k for the MAX1248 and higher than 100k for the MAX1249, where the internal reference is omitted. At VREF, the DC input resistance is a minimum of 18k. During conversion, an external reference at VREF must deliver up to 350A DC load current and have an output impedance of 10 or less. If the reference has higher output impedance or is noisy, bypass it close to the VREF pin with a 4.7F capacitor. Using the REFADJ input makes buffering the external reference unnecessary. To use the direct VREF input, disable the internal buffer by tying REFADJ to VDD. In power-down, the input bias current to REFADJ can be as much as 25A with REFADJ tied to V DD . Pull REFADJ to AGND to minimize the input bias current in power-down.
+3.3V 24k
MAX1248
510k 100k 9 REFADJ
0.01F
Figure 15. MAX1248 Reference-Adjust Circuit
OUTPUT CODE FULL-SCALE TRANSITION
11 . . . 111 11 . . . 110 11 . . . 101
Transfer Function
Table 7 shows the full-scale voltage ranges for unipolar and bipolar modes. The external reference must have a temperature coefficient of 20ppm/C or less to achieve accuracy to within 1LSB over the commercial temperature range of 0C to +70C. Figure 16 depicts the nominal, unipolar input/output (I/O) transfer function, and Figure 17 shows the bipolar input/output transfer function. Code transitions occur halfway between successive-integer LSB values. Output coding is binary, with 1LSB = 2.44mV (2.500V / 1024) for unipolar operation and 1LSB = 2.44mV [(2.500V / 2 - -2.500V / 2) / 1024] for bipolar operation.
FS = VREF + COM ZS = COM VREF 1024
1LSB = 00 . . . 011 00 . . . 010 00 . . . 001 00 . . . 000 01 (COM) 2 3 FS - 3/2LSB FS
INPUT VOLTAGE (LSBs)
Figure 16. Unipolar Transfer Function, Full Scale (FS) = VREF + COM, Zero Scale (ZS) = COM
18
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+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 MAX1248/MAX1249
Table 7. Full Scale and Zero Scale
UNIPOLAR MODE Full Scale Zero Scale Positive Full Scale VREF / 2 + COM BIPOLAR MODE Zero Scale COM Negative Full Scale -VREF / 2 + COM
VREF + COM
COM
OUTPUT CODE FS = VREF + COM 2 ZS = COM -FS = -VREF + COM 2 VREF 1LSB = 1024 R* = 10 +3V SUPPLIES +3V GND
011 . . . 111 011 . . . 110
000 . . . 010 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101
VDD 100 . . . 001 100 . . . 000 - FS *COM VREF / 2 COM* INPUT VOLTAGE (LSB) +FS - 1LSB * OPTIONAL
AGND
COM DGND
+3V
DGND
MAX1248 MAX1249
DIGITAL CIRCUITRY
Figure 17. Bipolar Transfer Function, Zero Scale (ZS) = COM, Full Scale (FS) = VREF / 2 + COM
Figure 18. Power-Supply Grounding Connection
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards. Wire-wrap boards are not recommended. Board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the ADC package. Figure 18 shows the recommended system ground connections. Establish a single-point analog ground (star ground point) at AGND, separate from the logic ground. Connect all other analog grounds and DGND to the star ground. No other digital system ground should be connected to this ground. For lowest noise operation, the ground return to the star ground's power supply should be low impedance and as short as possible.
High-frequency noise in the VDD power supply may affect the ADC's high-speed comparator. Bypass the supply to the star ground with 0.1F and 1F capacitors close to pin 1 of the MAX1248/MAX1249. Minimize capacitor lead lengths for best supply-noise rejection. If the +3V power supply is very noisy, a 10 resistor can be connected as a lowpass filter (Figure 18).
High-Speed Digital Interfacing with QSPI
The MAX1248/MAX1249 can interface with QSPI using the circuit in Figure 19 (fSCLK = 2.0MHz, CPOL = 0, CPHA = 0). This QSPI circuit can be programmed to do a conversion on each of the four channels. The result is stored in memory without taxing the CPU, since QSPI incorporates its own micro-sequencer. The MAX1248/MAX1249 are QSPI compatible up to their maximum external clock frequency of 2MHz.
______________________________________________________________________________________
19
+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 MAX1248/MAX1249
+3V +3V
1F 1 0.1F 2 3 4 5 6 7 +2.5V 0.1F 8 VDD CH0 SCLK 16 SCK PCS0 MOSI
ANALOG INPUTS
CS 15 MAX1248 CH1 MAX1249 DIN 14 CH2 CH3 COM SHDN VREF SSTRB 13 DOUT 12 DGND 11 AGND 10 REFADJ 9
MC683XX
MISO
(GND) CLOCK CONNECTIONS NOT SHOWN
Figure 19. MAX1248/MAX1249 QSPI Connections External Reference
TMS320LC3x Interface
Figure 20 shows an application circuit to interface the MAX1248/MAX1249 to the TMS320 in external clock mode. The timing diagram for this interface circuit is shown in Figure 21. Use the following steps to initiate a conversion in the MAX1248/MAX1249 and to read the results: 1) The TMS320 should be configured with CLKX (transmit clock) as an active-high output clock and CLKR (TMS320 receive clock) as an active-high input clock. CLKX and CLKR on the TMS320 are tied together with the MAX1248/MAX1249's SCLK input. 2) The MAX1248/MAX1249's CS pin is driven low by the TMS320's XF_ I/O port, to enable data to be clocked into the MAX1248/MAX1249's DIN. 3) An 8-bit word (1XXXXX11) should be written to the MAX1248/MAX1249 to initiate a conversion and place the device into external clock mode. Refer to Table 1 to select the proper XXXXX bit values for your specific application. 4) The MAX1248/MAX1249's SSTRB output is monitored via the TMS320's FSR input. A falling edge on the SSTRB output indicates that the conversion is in progress and data is ready to be received from the MAX1248/MAX1249.
XF CLKX
CS SCLK
TMS320LC3x
CLKR DX DR FSR
MAX1249
DIN DOUT SSTRB
Figure 20. MAX1248/MAX1249-to-TMS320 Serial Interface
5) The TMS320 reads in one data bit on each of the next 16 rising edges of SCLK. These data bits represent the 10 + 2-bit conversion result followed by four trailing bits, which should be ignored. 6) Pull CS high to disable the MAX1248/MAX1249 until the next conversion is initiated.
20
______________________________________________________________________________________
+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 MAX1248/MAX1249
CS
SCLK
DIN
START
SEL2
SEL1
SEL0
UNI/BIP SGL/DIF
PD1
PD0 HIGH IMPEDANCE B0 LSB HIGH IMPEDANCE
SSTRB
DOUT
MSB
B8
S1
S0
Figure 21. TMS320 Serial-Interface Timing Diagram
___________________________________________Ordering Information (continued)
PART MAX1248AEPE MAX1248BEPE MAX1248AEEE MAX1248BEEE MAX1248AMJE MAX1248BMJE MAX1249ACPE MAX1249BCPE
TEMP. RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C 0C to +70C 0C to +70C
PIN-PACKAGE 16 Plastic DIP 16 Plastic DIP 16 QSOP 16 QSOP 16 CERDIP* 16 CERDIP* 16 Plastic DIP 16 Plastic DIP
INL (LSB) 1/2 1 1/2 1 1/2 1 1/2 1
PART MAX1249ACEE MAX1249BCEE MAX1249AEPE MAX1249BEPE MAX1249AEEE MAX1249BEEE MAX1249AMJE MAX1249BMJE
TEMP. RANGE 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C
PIN-PACKAGE 16 QSOP 16 QSOP 16 Plastic DIP 16 Plastic DIP 16 QSOP 16 QSOP 16 CERDIP* 16 CERDIP*
INL (LSB) 1/2 1 1/2 1 1/2 1 1/2 1
Contact factory for availability of alternate surface-mount packages. * Contact factory for availability of CERDIP package, and for processing to MIL-STD-883B.
______________________________________________________________________________________
21
+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 MAX1248/MAX1249
_________________Pin Configuration
TOP VIEW
VDD 1 CH0 2 CH1 3 CH2 4 CH3 5 COM 6 SHDN 7 VREF 8 16 SCLK 15 CS 14 DIN
___________________Chip Information
TRANSISTOR COUNT: 2554
MAX1248 MAX1249
13 SSTRB 12 DOUT 11 DGND 10 AGND 9 REFADJ
DIP/QSOP
________________________________________________________Package Information
QSOP.EPS
22
______________________________________________________________________________________
+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 MAX1248/MAX1249
___________________________________________Package Information (continued)
PDIPN.EPS
______________________________________________________________________________________
CDIPS.EPS
23
+2.7V to +5.25V, Low-Power, 4-Channel, Serial 10-Bit ADCs in QSOP-16 MAX1248/MAX1249
NOTES
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1998 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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